1. Field of Invention
The present invention relates to a phase detector. More particularly, the present invention relates to a delay-locked loop circuit.
2. Description of Related Art
Recently, with the outstanding improvement of the semiconductor process, the operating frequency of the VLSI circuits has increased a lot. The high-speed systems, such as wireless phones, optical fiber links, microcomputers, and high-end system-on-a-chip (SOCs), reach the GHZ level. Therefore, the electronic devices need to upgrade their operating frequency in order to keep up with the improved semiconductor process. Furthermore, since a lot of circuits are integrated on a chip, the clock signal is entirely distributed on the chip, and the clock skew problem arises as a result.
For example, when an input clock drives a chip, an uncertain delay appears between the input clock and the internal clock, which makes the chip work incorrectly. In order to synchronize the system clock and suppress the clock skew of the chip, the phase-locked loop (PLLs) and delay-locked loop (DLLs) have been applied in many high-speed circuits and systems.
FIG. 1 shows a block diagram of the conventional DLL. The DLL includes a voltage-controlled delay line 107 (VCDL), a phase detector 101 (PD), a loop filter 105 (LF), and a charge pump 103 (CP). The PD 101 detects the phase difference between the internal clock and the input clock. The LF 105 is usually implemented with a single capacitor, which is charged/discharged by the CP 103, to reduce the high-frequency noises and provide a constant dc level to the VCDL 107.
The output signals of PD 101 (UP and DN) are integrated to the CP 103 and LF 105 to generate a control voltage (VCTL) for the delay line 107. When the circuit is locked, VCTL is a constant and the VCDL 107 finds the optimum path so that the input clock and the internal clock can be synchronized.
However, in this conventional DLL, the control voltage VCTL cannot keep up with the UP/DN signal when the UP/DN signal changes rapidly, which makes the DLL unstable. As a result, the entire circuit on the chip is unstable as well.
Therefore, there is a need for a new delay-locked loop and a stabilization method thereof which can be stable under the high speed operation condition.